At high operating frequencies, field effect transistor (FET) devices are typically manufactured on substrate material of gallium arsenide (GaAs) or gallium nitride (GaN). Though other materials may be used, GaAs or GaN is a higher quality material designed and controlled to provide good performance of FET devices. However, in addition to being higher quality materials than the other possible materials, GaAs and GaN are also more expensive and more difficult to manufacture. Unfortunately, in the typical chip configuration, the majority of the chip area includes integrated passive components, such as a matching structure. These passive components do not benefit from the higher quality substrate material, resulting in inefficient use of the chip layout.
With reference to prior art FIG. 1, a typical die 100 comprises a substrate 101 having active components and passive components. In an exemplary embodiment, die 100 is a monolithic microwave integrated circuit (“MMIC”). For example, die 100 may comprise a MMIC used in a power amplifier. Most of the space on die 100 is taken up by the passive components, such as a matching structure 110 and/or some interconnect features. A lesser amount of space is covered with active components, such as FET devices 120 located in areas designated by reference number 121. In the embodiment illustrated in FIG. 1, the areas 121, containing active FET devices 120, consume less than 10% of the area of die 100, and passive components cover the remaining area.
The FET devices 120 of FIG. 1 may comprise interdigital FETs common to those skilled in the art or folded FETs. The FET devices 120 and matching structure 110 are typically on the same substrate 101, as shown here. Integrating matching structure 110 on the same substrate as FETs 120 has the benefit of reducing associated parasitics and removing any interface between the FET and the corresponding integrated matching structure. This results in a high level of repeatability, which is necessary at high frequencies of operation. The high repeatability is desirable in order to achieve required performance levels and reduce the need to tune the circuit. Similarly, circuit parasitics increase as the operating frequency of the circuit increases. Thus, the prior art teaches towards integrating the matching structure and other functionality onto the MMIC (i.e., onto a single substrate).
Furthermore, and with continued reference to prior art FIG. 1, typical GaAs substrate 101 is often thinned to enhance thermal performance and to provide improved microwave performance at high frequencies. Thinning substrate 101 for high frequency performance is often used to prevent higher order mode propagation. For example, preventing propagation in modes other than common quasi-TEM microstrip modes.
Additionally, in general chip designs, multiple transistors are manufactured on the same substrate. Due to the integrated nature of the transistors, if even one transistor on the chip does not work properly, then the entire chip is compromised and cannot be used. Various types of transistors have different manufacturing success rates, referred to as the yield. Since multiple transistors are manufactured on the same substrate, the overall yield (also referred to as the rolled yield) of the substrate is the joint probability of producing N good FETs simultaneously on the same chip. In other words, if the probability of producing a single good FET is 99%, then the probability of producing a chip having N good FETs is 0.99N. For example, the probability of producing a chip with 46 good FET devices at this yield is 0.9946=63%. In many cases, the individual yield for a particular type of FET is less than 99%. As one can appreciate, as the number of FETs on a chip increases, the probability of producing a working FET device decreases. The rolled yield issue can significantly limit the size and complexity of circuits, especially if the individual FET yield is lower than 99% by only a few percentage points.
Thus, a need exists for improved chip layouts and designs which result in more efficient use of the chip space for active components. Furthermore, a need exists for avoiding rolled yield issues when integrating large number of FETs in a complex circuit.